Two Routes to Fewer Qubits: How qLDPC Codes and Erasure Qubits Attack Quantum Computing's Overhead Problem

Fault-tolerant quantum computing faces a significant overhead problem, requiring vast numbers of physical qubits for each logical qubit. Two promising strategies, qLDPC codes and erasure qubits, offer distinct paths to reduce this physical-to-logical qubit ratio and advance quantum computing.

Yasmin Haddad

November 2, 2026 · 6 min read

Fault-tolerant quantum computing has a scaling problem that sits at the heart of the field: quantum states are fragile, and correcting their errors consumes enormous hardware resources. Depending on the error-correction scheme and the underlying hardware error rates, building a single reliable logical qubit can demand somewhere between 100 and 10,000 physical qubits. Those estimates, while imprecise, define the central barrier to useful quantum machines — a machine that would otherwise need thousands of logical qubits balloons into one requiring millions of physical ones.

Two strategic responses have emerged. One optimizes the mathematics: quantum low-density parity-check (qLDPC) codes promise the same fault tolerance from a far smaller physical-qubit budget. The other optimizes the hardware itself: erasure qubits re-engineer the physical device so its most common failure becomes the easiest kind of error to correct. This article explains both mechanisms and compares their distinct philosophies.

Advanced Codes: Optimizing Software with qLDPC

The traditional workhorse of quantum error correction is the surface code, which arranges qubits on a two-dimensional lattice and repeatedly measures local check operators to detect errors. Surface codes are prized for their tolerance of noisy hardware, but they pay for that robustness with a low encoding rate: only a small fraction of the physical qubits in a surface-code patch contribute to the logical qubit being protected, so the physical-to-logical ratio grows steeply as a machine scales.

Quantum LDPC codes attack the problem at the level of code structure rather than qubit physics. By designing codes whose parity checks are sparse — each check involving only a few qubits — theorists can pack more logical qubits into the same physical footprint while preserving the distance properties that make error correction possible. According to The Quantum Insider, which surveyed recent progress in error-correction strategies, recent theoretical and experimental work suggests qLDPC codes could achieve fault tolerance with significantly fewer physical qubits per logical qubit than surface codes, potentially cutting resource requirements by an order of magnitude or more.

The claim has already moved beyond theory in at least one commercial case. Iceberg Quantum, a Sydney-based startup founded by University of Sydney researchers, unveiled its Pinnacle fault-tolerant architecture in February 2026. The company claims the design can reduce the physical qubits needed to break RSA-2048 encryption from more than a million to under 100,000 — a tenfold reduction under standard hardware assumptions. That figure is a company claim about a specific architecture, not a measured experimental result, and it depends explicitly on those stated assumptions. Even so, it illustrates why qLDPC has become one of the most closely watched directions in the field: the gains arrive by changing the code, not by demanding more from the qubits themselves.

The trade-off is conceptual as well as practical. qLDPC codes are more intricate mathematical objects than surface codes, and their advantages in encoding density must be weighed against the complexity of implementing their longer-range connectivity and decoding algorithms on real devices. The strategy's core principle, though, is simple to state: keep the hardware as it is, and make every physical qubit do more logical work.

Hardware Innovations: Engineering Erasure Qubits

The second strategy starts from a different observation: not all errors are equally hard to correct. In standard error correction, a qubit can fail in arbitrary, unknown ways, and the decoder must infer both what went wrong and where. But classical coding theory long ago identified a friendlier failure mode — the erasure — in which the location of the loss is known, and only the recovery must be worked out. Correcting an error whose position is already flagged is substantially cheaper than correcting an unidentified one.

Erasure qubits are hardware engineered to convert their dominant physical noise into exactly this friendlier form. A recent technical perspective on developments in superconducting erasure qubits, published on arXiv, explains the mechanism: in dual-rail encodings, a qubit's information is stored redundantly across two modes, so that amplitude damping — the most common decay process in superconducting circuits — does not corrupt the logical state arbitrarily but instead destroys one of the rails in a detectable way. The physical error is thereby converted into a flagged erasure, which the authors argue leads to improved logical error rates and higher noise thresholds for the codes running on top of such hardware.

Crucially, the perspective notes that this bias toward erasure noise does not require a more complex control infrastructure. In a coaxial dual-rail implementation, the architecture differs from a conventional transmon only in the fabrication of an alternative qubit design, while the physical footprint and control wiring remain unchanged — a property the authors describe as making the infrastructure significantly more scalable. Because the modification is at the device-fabrication level, the benefits are not contingent on some distant generation of hardware: the authors argue that engineering erasure qubits enables immediate advantages for current and near-term devices in the NISQ (Noisy Intermediate-Scale Quantum) era.

The arXiv document is explicitly framed as a perspective outlining key concepts and reviewing recent theoretical and experimental progress across academic and industrial groups — not as a report of a single completed demonstration. Its core principle, though, mirrors the qLDPC logic in reverse: rather than changing the code to tolerate the hardware's noise, change the hardware so its noise becomes easier for any code to tolerate.

Comparing Hardware-Efficient QEC Strategies

Setting the two approaches side by side reveals that they are not competing answers to the same question but complementary answers to two different questions — one about how information is encoded, the other about how it fails. The table below categorizes each strategy by where it intervenes and what efficiency it pursues.

Two philosophies for reducing the physical-to-logical qubit ratio
Approach	Core Principle	Example	Goal for Efficiency
Advanced codes (qLDPC)	Optimize the mathematical structure of the error-correcting code itself, so fewer physical qubits encode each logical qubit	Iceberg Quantum's Pinnacle architecture (unveiled February 2026), claiming under 100,000 physical qubits to break RSA-2048 versus more than a million with conventional codes	Higher encoding efficiency and fault tolerance with order-of-magnitude-fewer physical qubits per logical qubit than surface codes
Engineered hardware (erasure qubits)	Modify the physical qubit's noise characteristics so dominant errors become detectable erasures rather than arbitrary corruptions	Dual-rail superconducting qubits that convert amplitude damping into erasures, fabricated with unchanged footprint and wiring relative to a conventional transmon	Improved logical error rates and higher noise thresholds, with benefits available to near-term NISQ-era devices

Two philosophies for reducing the physical-to-logical qubit ratio

Approach

Core Principle

Example

Goal for Efficiency

Advanced codes (qLDPC)

Optimize the mathematical structure of the error-correcting code itself, so fewer physical qubits encode each logical qubit

Iceberg Quantum's Pinnacle architecture (unveiled February 2026), claiming under 100,000 physical qubits to break RSA-2048 versus more than a million with conventional codes

Higher encoding efficiency and fault tolerance with order-of-magnitude-fewer physical qubits per logical qubit than surface codes

Engineered hardware (erasure qubits)

Modify the physical qubit's noise characteristics so dominant errors become detectable erasures rather than arbitrary corruptions

Dual-rail superconducting qubits that convert amplitude damping into erasures, fabricated with unchanged footprint and wiring relative to a conventional transmon

Improved logical error rates and higher noise thresholds, with benefits available to near-term NISQ-era devices

The contrast in mechanisms is the heart of the comparison. qLDPC accepts the hardware's noise as given and restructures the code so the same noise is corrected with less redundancy; the projected savings are largely theoretical or architectural, exemplified by Iceberg's tenfold-reduction claim under standard hardware assumptions. Erasure qubits accept the code as given and restructure the noise, exploiting the fact that a flagged loss is intrinsically cheaper to correct than a silent one — and because dual-rail fabrication leaves footprint and wiring unchanged, the gains are described by the arXiv perspective as available immediately rather than behind a scaling breakthrough.

Neither strategy is free of caveats. qLDPC's headline numbers come with "standard hardware assumptions" attached and, in the Pinnacle case, from a startup describing its own architecture. Erasure qubits' promise of improved logical error rates and higher thresholds rests on a body of theoretical and early experimental work that the perspective itself characterizes as ongoing across both academic and industrial groups. The two also combine naturally rather than compete: a noise-biased, erasure-friendly hardware layer makes any code's job easier, including a qLDPC one. Declaring a winner would misrepresent a field in which both principles are being pursued in parallel precisely because they attack the overhead problem from different ends.